Preparation and characterization of field effect transistor with (Bi,La)Ti3O12 ferroelectric gate material

Abstract

For application in a ferroelectric random access memory, capacitors with structures of Pt/(Bi, La)Ti3O12 (BLT)/Pt and Pt/BLT/Y2O3 film layers on Si(100) substrates were prepared by the solgel method, and BLT FET devices were fabricated by using Y2O3 as buffer layer. A Pt/BLT/Pt/Si capacitor showed no critical degradation in polarization values after retention read pulses input for 10(5.5) s. The capacitance-voltage data of the Pt/BLT/Y2O3/Si capacitors at input voltage of 5 V indicate that the memory window voltage decreased from 1.4 V to 0.6 V with increasing annealing temperature from 700 C to 750 C. From the drain current as a function of gate voltage (VG) for Pt/BLT/Y2O3/Si(100)-FET devices, the memory window voltage increased from 0.3 V to 0.8 V as VG increased from 3 V to 5 V.