Ultra-low power 1T-DRAM in FDSOI technology
- Authors
- El Dirani, H.; Lee, K. H.; Parihar, M. S.; Lacord, J.; Martinie, S.; Barbe, J-Ch.; Mescot, X.; Fonteneau, P.; Broquin, J. -E.; Ghibaudo, G.; Galy, Ph; Gamiz, F.; Taur, Y.; Kim, Y. -T.; Cristoloveanu, S.; Bawedin, M.
- Issue Date
- 2017-06-25
- Publisher
- ELSEVIER
- Citation
- MICROELECTRONIC ENGINEERING, v.178, pp.245 - 249
- Abstract
- A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z(2)-FET memory cell features a large current sense margin and small OFF-state current at 25 degrees C and 85 degrees C. Moreover, low power consumption during state '1' writing is achieved with similar to 0.5 V programming voltage. These specifications make the Z(2)-FET an outstanding candidate for low-power eDRAM applications. (C) 2017 Elsevier B.V. All rights reserved.
- Keywords
- CAPACITORLESS 1T-DRAM; GATE; Z(2)-FET; DEVICES; CAPACITORLESS 1T-DRAM; GATE; Z(2)-FET; DEVICES; Fully Depleted Silicon-On-Insulator (FDSOI); Sharp switch; Z(2)-FET; Low-power; Embedded memory; 1T-DRAM
- ISSN
- 0167-9317
- URI
- https://pubs.kist.re.kr/handle/201004/122613
- DOI
- 10.1016/j.mee.2017.05.047
- Appears in Collections:
- KIST Article > 2017
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